CCLKSEL=SYSCLK_IS_USED_AS_TH
CPU Clock Selection register
| CCLKDIV | Selects the divide value for creating the CPU clock (CCLK) from the selected clock source. 0 = The divider is turned off., no clock will be provided to the CPU. This setting should typically not be used, the CPU will be halted and a reset will be required to restore operation. 1 = The input clock is divided by 1 to produce the CPU clock. 2 = The input clock is divided by 2 to produce the CPU clock. 3 = The input clock is divided by 3 to produce the CPU clock. … 31 = The input clock is divided by 31 to produce the CPU clock. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| CCLKSEL | Selects the input clock for the CPU clock divider. 0 (SYSCLK_IS_USED_AS_TH): Sysclk is used as the input to the CPU clock divider. 1 (THE_OUTPUT_OF_THE_MA): The output of the Main PLL is used as the input to the CPU clock divider. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |